Projects
기존 포트폴리오에서 내용만 가져와 블로그형 프로젝트 아카이브로 재구성했습니다.
광소자 · 회로설계
Sep-Nov 20244x4 active-matrix pixel array in 110nm CMOS, optimized 4T pixel geometry, integrated CDS, and implemented ADC/SRAM readout chain for full-frame acquisition.
SNR 24.62 dB | SPICE validation회로설계
May-Jun 20248-state binary-coded FSM on Basys3 using primitive gates, D/JK flip-flops, and ripple-counter debounce clocking. Met 50MHz timing with under 220 LUT usage.
Verilog + Vivado + hardware verification회로설계
May-Jun 202411-module hierarchical FSM with custom clock dividers and variable counters for intro, climb, bridge, and fast-blink animation sequences.
12-bit time-division multiplexing | parallel logic trees회로설계
20248-state, 4-input AFSM with seven-segment real-time location display, implemented across Verilog/Vivado and transistor-level Cadence design styles: LBD, FCD, PLD.
LVS-clean full-chip layout delivered회로설계
Nov-Dec 202418-state converter with additional-state memory to reduce bit circulation and output logic fan-in. Mixed NSL(FCD)+OL/MUX(PLD) layout strategy.
50%+ short-circuit power reduction | 819um2 core자동화 · 광소자
Sep-Nov 2025Python Streamlit app automating transfer/output curve analysis and extracting Vth, SS, DIBL with report generation and output characteristic prediction.
Streamlit + Plotly + NumPy + SciPy + scikit-learn자동화
Jul-Aug 2024Automated truth-table scraping and logic minimization pipeline producing optimized Verilog and timing diagrams for rapid design workflow.
Excel automation + LLM-assisted synthesis연구노트
Feb 2026-PresentIndependent research on learning deviations between theoretical current equations and measured I-V data to derive corrected empirical predictive formulations.
Process variation-aware modeling